With improvement of performance of information processing apparatus or the like, data rate of signals transferred within the apparatus or between the apparatuses becomes high, and a clock and data recovery (CDR) circuit which reproduces a clock and data from a received data signal is used in the communication circuit of a receiving side. In order to evaluate the quality of a product when such a communication circuit is made into a product, a test related to a bit error rate (BER) is performed. A test technique related to the bit error rate includes, for example, a bath tub test in which the detection phase of data is swept while the CDR circuit is kept in a locked state and the bit error rate at each detection phase and amplitude of data is obtained, an eye-monitor.
For example, in a receive data signal depicted in FIG. 13A, transition timing of data changes randomly in actual communication by jitter, noise in the time axis, and by noise in the voltage axis and so on, as depicted in FIG. 13B. It is possible to evaluate the operating margin by an eye diagram obtained by sweeping the phase of the data in a state where a boundary is kept constant as depicted in FIG. 13C. For example, it is possible to obtain a permissible amount of displacement of a detection phase of the data from the optimum sampling point. In FIG. 13C, the lateral direction indicates a detection phase of data in 1 UI (unit interval), the vertical direction indicates the threshold voltage of data decision, and a region “eye” indicates a region in which data may be detected with accuracy. As stated above, as a result of obtaining the bit error rate in each phase by sweeping the detection phase of the data, it is possible to check whether or not the present detection phase of data is optimum, or how much margin a sample time has.
There exists a CDR circuit in which the existence of an error in the sampled data is detected by changing a phase of an extraction clock outputted from a phase interpolator or a threshold value level of a sampling circuit, so that operation margin in time and voltage is measured (for example, see Patent Document 1). There exists a semiconductor device in which an eye-opening margin of the receive data, which includes a jitter component of a CDR circuit, is evaluated in a receiver circuit of high-speed serial data of a parallel clock system (for example, see Patent Document 2). There exists a technique in which the phase of a clock signal is adjusted based on a phase adjustment signal for adjusting the detection timing of data, to which an offset is added, and the detection timing of data is displaced in time in correspondence with the offset, to perform a jitter tolerance test (for example, see Patent Document 3).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2007-184847
[Patent Document 2] Japanese Laid-open Patent Publication No. 2009-212992
[Patent Document 3] Japanese Laid-open Patent Publication No. 2008-72319
Configuration examples of CDR circuits are depicted in FIG. 14A and FIG. 14B, the CDR circuit has a function to allow for sweeping of the detection phase of the data in a state where the boundary is kept constant, to realize a bath tub test or eye-monitor. FIG. 14A depicts an example of a phase-interpolation-type CDR circuit. In FIG. 14A, reference number 202 indicates a phase detection circuit, reference number 203 indicates a low-pass filter, reference number 204 indicates an interpolation code generation circuit, reference numbers 205 and 206 indicate phase interpolation circuits, reference number 207 indicates an adder, reference number 208 indicates a sampling circuit, reference number 209 indicates a bit error rate detection circuit, and reference number 210 indicates a transmission path. FIG. 14B depicts an example of a data-interpolation-type CDR circuit. In FIG. 14B, reference numbers 212 and 219 indicate data interpolation switched capacitor circuits, reference numbers 213 and 220 indicate comparators, reference number 214 indicates a demultiplexer, reference number 215 indicates a phase detection circuit, reference number 216 indicates a low-pass filter, reference number 217 indicates an interpolation code generation circuit, reference number 218 indicates an adder, reference number 221 indicates a bit error rate detection circuit, and reference number 222 indicates a transmission path.
Usually, in order to realize a bath tub test or eye-monitor, two circuits related to interpolation are used in either of the phase-interpolation-type CDR circuit or the data-interpolation-type CDR circuit, as indicated in FIG. 14A and FIG. 14B. Since a general phase-interpolation-type CDR circuit 201 originally uses two phase-interpolation circuits 205, 206 for loop and data sampling, the number of circuits which must be added for realizing a bath tub test or eye-monitor is small. However, it is difficult to produce the phase-interpolation-type CDR circuit such as one depicted in FIG. 14A to cope with a wide frequency range. In contrast, it is not difficult to produce the data-interpolation-type CDR circuit such as one depicted in FIG. 14B to cope with a wide frequency range. However, since the general data-interpolation-type CDR circuit 211 usually uses one data interpolation switched capacitor circuit 212, one more data interpolation switched capacitor circuit 219 must be added in order to realize a bath tub test or eye-monitor. Since a data interpolation switched capacitor circuit has a large circuit area, a circuit area of a CDR circuit is increased and a cost is increased.